Monolithic integration of MEMS/NEMS and electronics offers significant benefits enabling high volume production driving down the per-unit costs of sensor and actuator systems significantly. Micromechanical transducer systems not only need to receive analog and digital electrical inputs and transmit the output, but should also be able to measure rotation, strain, temperature, pressure, acceleration, infrared radiation, micro fluidic chemical properties of liquids and gasses. Effective integration offers other benefits, including, simplifying interconnect issues, reduced packaging and fabrication complexity and significantly improving the overall performance and ease of use for the device.
One method of monolithic integration of CMOS and MEMS is to modify the complementary metal-oxide semiconductor (CMOS) foundry facility to fabricate micromechanical structures. Some of the commonly used micromechanical (MEMS) mechanical structures like polysilicon, nitride etc require high-temperature processing during deposition and annealing to relieve stress and this cannot be performed on the same substrate in the presence of CMOS electronics due to the lower temperature limitation of the metals in CMOS. Another limitation of the method is that CMOS requires the substrate to be planar after the MEMS fabrication to achieve high-resolution features in the photolithographic process. Thus, the current CMOS-MEMS integration methodologies faces serious limitations, requiring sacrificing materials and allowing very little flexibility in device design.
Monolithic integration process may be divided into three classes: (1) Pre CMOS (2) Intermediate CMOS (3) Post CMOS. In prior art “pre CMOS” fabrication process methods, MEMS/NEMS structures are fabricated before the electronics are integrated. One example of this process is the micromechanics-first approach developed at Sandia National Laboratory by J. Smith et al. In this process a pre-etched trench is used to house the MEMS structures. After the fabrication of the desired MEMS structures, this housing is refilled with oxide, planarized using chemical-mechanical polishing (CMP), and finally sealed with a nitride membrane. Conventional CMOS processing was then carried out next to this MEMS area. This defined a CMOS device area and micromechanical device area on the same substrate as shown in FIG. 1. One of the disadvantages with this process is that it needs a dedicated production line and the process is complicated.
In the Intermediate CMOS fabrication process, the process flow between CMOS and MEMS is mixed in the sequence. Initially a part of the CMOS process is performed and then paused for additional thin film deposition or micromachining steps. Some of the commercially available sensors in this art include the Analog Devices integrated MEMS and Infineon's pressure sensor shown by C. Hierold. In the post CMOS process, MEMS/NEMS structures are fabricated after the CMOS or electronics is fabricated on the substrate. The disadvantage of this process is the temperature limitation of the process to below 400° C. to protect the aluminum in the electronics. This leads to the elimination of commonly used MEMS/NEMS high temperature materials like LPCVD polysilicon, silicon nitride etc.
An alternative approach to integration and packaging using high density interconnect (HDI) multichip modules (MCMs) was developed by researchers at GE Corporate Research and Development center as a “chips first” approach described in by W. Daum et al. as shown in FIG. 2. This process involves placing bare chips of MEMS test die and a generic CMOS electronics die into mechanically milled cavities on a base substrate and then fabricating the thin-film interconnect structure on top of the components. A computer-controlled argon ion laser system drills via holes through the polyimide film directly to the chip I/O pads. The interconnection metallization and via contacts were formed by a combined sputtering/electroplating process and patterned by computer-controlled adaptive laser lithography and etching. Some of the limitations with this process were the warping of the MEMS device due to excessive heating during the laser ablation step.
Prior art monolithic integration processes in this art involve utilizing complimentary metal-oxide semiconductor (CMOS) semiconductor layers to fabricate micromechanical structures is shown in U.S. Pat. No. 5,717,631, U.S. patent application Ser. No. 11/602,087, U.S. Pat. No. 6,060,336. Some of the major limitations with this approach involve the need to sacrifice MEMS/NEMS materials with various mechanical properties as commercial foundries cannot modify their processes to suit MEMS/NEMS. This also adds additional constraints when fabricating the MEMS/NEMS sensors or actuators as they would need to limit their processing techniques like etching, deposition so as to not harm the electronic circuits present on the substrate. Stress and other mechanical deficiencies may lead to device failure when the materials tailored to CMOS are modified as mechanical elements in MEMS.
Prior art hybrid MCM technology processes include putting one or several dies with different functionality into prefabricated trenches on a substrate, planarizing these chips, providing an insulator layer on top and forming electrodes have been demonstrated in U.S. Pat. Nos. 6,403,463, 6,780,696 B1, 6,154,366, 6,759,270. Some of the major drawbacks in these prior art references include semiconductor substrates like silicon that are fragile and the devices need to be repackaged resulting in significant costs.
The invention describes a method of manufacture for Monolithic hybrid integration of CMOS-MEMS with enhanced flexibility of using materials without hindrance to process parameters. This invention enables this integration effectively without the need to sacrifice the inherent strengths of both the CMOS or MEMS technologies and bringing about their fusion in a hybrid approach on a common substrate. This invention also allows the ability to effectively package the entire system after integration.
Several of the limitations mentioned above are overcome in the present invention which describes a method to effectively synergize CMOS-MEMS/NEMS functionality and finally package them creating a very cost effective, reliable, robust transduction system In the present invention, protective layers are coated on the substrate to protect either the CMOS device area in the “Post CMOS” process or the MEMS device area in the “Pre CMOS” process to prevent damage to the sensor or electronics. Oxygen plasma etching can be used to open the vias to access conductive layers, being precisely defined by photolithography instead of laser which is known to cause damage in some of the previous integration approaches.
Either the “Post CMOS” or “Pre CMOS” fabrication may be carried out on a semiconductor substrate without compromising on the individual technologies strength and then integrating CMOS if MEMS is already present or MEMS if CMOS is already present on the same substrate.
The invention provides an improved ability to effectively package an entire system using a glass, silicon, plastic or metal housing. Packaging provides physical protection against external scratching and breakage, environmental protection and any other external forces that may damage the leads or the sensors. Effective packaging of the integrated system leads to lower cost, improved reliability and improved performance. This invention addresses some of the important issues present in current packaging methodologies. As one specific example related to reliability issues with plastic packages, the Thermal coefficient of expansion (TCE) mismatch resulting from the curing of the resins as they shrink in volume, creates a large temperature differential resulting in large strain mismatch, damaging the wire bonds. This issue can be eliminated or reduced significantly in the present invention as there will be no wire bonds involved and the fabrication is planar and the metal traces can be more effectively protected. The packaging methodology from the current invention also eliminates the need for solder bumps for integration of CMOS-MEMS and packaging. The invention also provides a method to further encapsulate the entire system by adding a secondary protective layer of organic materials providing a very effective packaging methodology.